An All-Digital PLL Proposal using Gain Control
Technique
ABSTRACT
Time-to-digital converter (TDC) has been the
main technique used in all-digital phase-locked loops
(ADPLL). However, this approach has several design
issues, and the solutions to resolve them always in-
crease the complexity of the system. In this paper,
an alternative method for handle the frequency er-
ror detection using a type II ADPLL architecture
is presented. The proposed technique does not per-
form direct conversion from time to digital, but em-
ploys the discrete-time processing of compared signals
from phase error detection. This architecture has the
advantage of scalability and integration of all-digital
techniques and has less complexity than conventional
ADPLLs. The derivation of equations for the pro-
posed architecture and its noise analysis is provided.
The results are validated through system level simu-
lations using macro-models of the devices. The result
of the transient simulation shows the theoretical pre-
dictions about the trajectory of output frequency.

Fábio Grigollo received the B.S. de-
gree in Information Technology from
Federal University of Juiz de Fora and
major in Business Intelligence in 2012,
Brazil. He received the M. S. degree
from International Iberoamerican Uni-
versity in 2014. His research interest
includes business intelligence and data
mining algorithms.